The present invention relates to the method of producing a complementary Metal Insulator Semiconductor filed effect transistor (hereinafter, referred to as "CMOS transistor").
In the conventional method of producing a CMOS transistor, ion implantation technology is utilized to dope N type impurity and P type impurity into a semiconductor substrate so as to form a pair of N type source and drain regions and another pair of P type source and drain regions.
However, according to the ion implantation technology, since the doped impurities have a depth profile of density in the form of Gaussian distribution, the impurities are distributed broadly in the depth direction. Therefore, the impurity distribution cannot be confined in a relatively shallow portion of the semiconductor material, thereby causing problem that scaling-down of the device cannot easily be performed. Since the source and drain regions formed by the ion implantation have a relatively great junction depth, the CMOS transistor device cannot be operated satisfactorily at submicron channel length.